1. Field of the Invention
This invention relates to an improved structure for a semi-conductor device and methods for using such a device.
2. Discussion of Prior Art
Over the last two decades there has been much interest in semiconductor devices which operate by restricting the motion of current carriers in one or more directions. In such devices the carriers can only occupy a discrete set of energy levels or sub-bands in one or more dimensions. The motion of the carriers is said to be quantised in the direction of confinement.
In heterojunctions, formed by the joining together of two semiconductor compounds of different band gaps, the carriers are confined to a potential or quantum well. A two dimensional electron gas is formed if the carriers are electrons (or a two dimensional hole gas is formed if the majority carriers are holes).
One particular type of semiconductor device which has been fabricated, typically from GaAs, is the single electron transistor which was invented in 1987. In this device the potential well is of such a size that it can hold only a few electrons (typically between 0 and 20). Furthermore, once this number is fixed (by an external contact potential) it does not fluctuate in time by more than one electron.
Such devices are confined to operate at low temperatures (typically less than liquid nitrogen temperatures) due to the physics which allows them to function. The devices rely on the fact that the potential well has a small capacitance, and the energy that it takes for electrons to charge this well is quite large. If the device is cooled to low temperatures the electron thermal energy becomes less than the charging energy. Without a significant source-drain voltage bias the electrons cannot travel through the potential well. This is known as Coulomb blockade.
According to a first aspect of the invention there is provided a field effect single electron transistor fabricated from a narrow band gap semiconductor.
Single Electron Transistors (SET) have the highest charge sensitivity of any man-made device. The SET is suited for applications where it is necessary to measure small fluctuations of charge without disturbing the system under study, or for providing low power transistor action. They also have potential for sensitive detectors of pressure, acceleration and temperature at least. Other detectors may be envisaged.
The transistor of the first aspect of the invention may be referred to as a Zener single electron transistor (Zener SET). Prior art transistors can be referred to as unipolar single electron transistors.
Zener SETs are advantageous because they are potentially simpler to fabricate and control, they may operate at higher temperatures than prior art devices, both n-type and p-type devices may be fabricated, and confinement may be enhanced due to the low effective mass of conduction electrons in p-type devices.
Further advantages of single electron transistors are that they are physically small (e.g. nanoscale) when compared to conventional field effect transistors resulting in a higher packaging density though lower power density.
The transistor preferably contains a heterojunction between layers of a first and a second material. The first material may be InSb or CdxHg1xe2x88x92xTe.
The second material may be InAISb or CdTe or CdxHg1xe2x88x92xTe. The heterojunction may be provided as a single layer of first material adjacent to a single layer of second material. Alternatively, the heterojunction may be provided as a single layer of first material between two layers of second material.
Should the heterojunction be provided as a single layer of first material adjacent to a second material, the second material may be an oxide (i.e. may be an insulator) or may be a semi-conductor. The first material may be considered a narrow band gap semiconductor. In the cases wherein the second material is a semi-conductor it may be considered a wide band gap semi-conductor. Other materials may be suitable for the first and second materials.
The skilled person will realise that should the first material be CdxHg1xe2x88x92xTe the band gap can be tailored to any desired value by adjusting the value of x. As x tends to ≅0.15 the band gap of the material tends to zero. However, x may be chosen to be an optimal value.
Should the second material be CdxHg1xe2x88x92xTe the value of x may be chosen to tend to one (that is CdTe). CdTe is preferred for its electronic properties but may not be achievable in view of other physical considerations: for example crystal growth considerations and lattice mismatch.
There may be provided on a first side of the heterojunction a third material which may be provided as a layer. The third material may function as a first gate electrode. The third material may be a metal. It may be Al or Au, or may be any other suitable conductor. Such a structure is advantageous because the presence of the gate electrode allows the electron/hole gas to be controlled within the heterojunction.
A second gate electrode may be provided on a second side of the heterojunction which is on the opposite side of the heterojunction from the first side. The second gate electrode may be fabricated from a metal. Such a structure in combination with the first gate electrode allows the electron/hole gas to be controlled.
The second gate electrode may be insulated from the materials forming the heterojunction by at least a single layer of insulation. An insulation layer is advantageous in that it modifies the interaction between the second gate electrode and the heterojunction in such a way as to give the desired functionality.
At least one (and preferably two) side gate may be provided. These may help to control the electron/hole gas in the desired manner.
The side gates may be insulated from the materials forming the heterojunction by a layer of insulation.
The side gate may comprise an elongate area along one side of the first or second material above the heterojunction. Preferably when two side gates are provided each forms an area along a side of the first or second material which sides are opposite each other. The areas may be rectangles. Most preferably the two side gates are in the same plane and there exists a gap within that plane between the two areas of side gates. The side gates preferably extend generally parallel to each other.
Preferably, the second gate electrode is provided above and may be insulated from the side gate. Again such a structure allows the electron/ hole gas to be controlled in the desired manner.
The insulation may be silicon dioxide SiO2 or any other suitable insulation material. Indeed, different types of insulation material may be used for different layers of insulation. Or indeed, the layers of insulation separating the materials of the heterojunction and the side gate may be the same as the layers of insulation separating the side gate from the second gate electrode.
Preferably the second gate electrode comprises a primary portion which extends over the gap between the side gates. Such a structure may have a large influence in the electrons in the electron/hole gas.
The second gate electrode may have a first broad region connected to a second broad region via a narrower waist region. The second gate electrode may be a bow tie shape possibly with the central, waist, portion of the bow tie extending over the gap between the side gates.
The skilled person will appreciate that the effect of the side gate electrodes may be thought of as creating a quantum wire wherein electrons or holes are held by an applied electric field in a narrow strip within the electron sheet. The use of electrodes to form the quantum wire may be thought of as soft confinement.
An alternative, or additional, way of forming the quantum wire may be with hard confinement as opposed to through the provision of side gates (soft confinement).
In one embodiment the heterojunction may be provided between a strip of first material and a layer of second material. That is the width of the first material may be much less than the width of the second material. This potentially provides a hard confined quantum wire. The first and second materials may be as described in relation to the embodiments hereinbefore. In particular the first material may be thought of as a narrow band gap semi-conductor and the second material may be thought of as a wide band gap semi-conductor.
The strip of narrow band gap semi-conductor may have a width of substantially 50 nm. However, the strip may have a width substantially in the range 10 nm to 90 nm. More preferably the width of the strip may be substantially in the range 25 nm to 75 nm.
In this embodiment a second gate electrode may be provided overlying the strip of narrow band gap semi-conductor. The second gate electrode may or may not overlie regions of the wide band gap semi-conductor where no narrow band gap semi-conductor is present. Preferably the second gate electrode has the bow tie structure discussed hereinbefore.
Preferably the second gate electrode is separated from the semi-conductor materials by a layer of insulator which may be silicon dioxide.
The narrower waist region of the second gate electrode may have a width of substantially 50 nm. However, the narrower waist region may have a width substantially in the range 10 nm to 90 nm. More preferably the width of the narrower waist region may be substantially in the range 25 nm to 75 nm. The skilled person will appreciate that this may form a region where the second gate electrode overlies the narrow band gap semi-conductor which is substantially square having a side of substantially 50 nm.
In an alternative embodiment the quantum wire may be provided by the V-Groove method for fabricating quantum wires. This may be preferred over the method of providing a thin strip of narrow band gap semi-conductor because the confinement offered may be cleaner.
The transistor may contain a V shaped notch or groove within a substrate layer.
A layer of second material may be provided lining the groove. The layer of second material may also form a V shaped notch or groove. A region of first material may be provided in the V of the notch in the second material.
The notch may be substantially filled with a layer of insulation. However, the notch may be partially filled with insulation such that the first material is covered. The insulation may cover the region of first material. Preferably a second gate electrode is provided on top of the layer of insulation. Preferably the second gate electrode has a bow tie shape having a primary portion as described hereinbefore. The primary portion of the second gate electrode may overlie the region of first material. A plurality of quantum wires may be provided in a single groove. The wires may be stacked one above the other.
In yet another embodiment the transistor may have a layer of second material having a non planar surface upon which a quantum wire has been fabricated.
The substrate may have a surface which is stepped (i.e. has a plurality of steps) due to being cut off axis. That is off-axis to a material lattice plane having atoms aligned to form a smooth surface. The angle of a plane of the stepped surface of the substrate may be adapted to provide a specified distance between steps. The distance may be in the range 0.1 xcexcm to 1 xcexcm. The skilled person will realise the more acute the angle the longer the distance between the steps.
Regions of first material may be provided in regions associated with the steps in the second material. The regions of the first material may be covered with an insulator. The insulator may also cover the surface of the second material where there is no first material provided. It will be appreciated by the skilled person that when fabricating quantum wires by such a method the thin layer of the first material may cover the entire non planar surface of the second material with regions being concentrated in regions associated with the steps.
A second gate electrode may be provided on top of the layer of insulation overlying the regions of first material. The gate may have substantially the dimensions as discussed hereinbefore.
The second gate electrode may overlie a number of regions of first material. The regions of first material may be considered to be quantum wires.
In yet another embodiment the transistor may comprise at least one ridge grown quantum wire. The ridge grown quantum wire may include reverse mesa etched from a substrate. Ridges in-between the reverse mesa may have a layer of second material provided upon a surface. On a surface region of the layer of second material there may be provided a region of first material.
A second gate electrode may be provided overlying the region of first material and the second gate electrode may be separated from the first material be a layer of insulation.
The transistor may be thought of as providing a controllable single potential maxima or minima along a quantum wire. That is providing a quantum dot within a quantum wire.
The various techniques for forming quantum wires are disclosed in the PhD thesis of Matthew John Steer, dated October 1997, entitled xe2x80x9cOptical and Structural Characterisation of III-V Semiconductor Quantum Wires and Quantum Dot Structuresxe2x80x9d from the University of Sheffield. This thesis is incorporated by reference and the skilled person is directed to read this thesis.
At a third and fourth end of the transistor (which are at opposite ends of a plane parallel with the first and second sides) there may be provided a drain and a source electrode. The drain and source electrodes allow a bias voltage to be applied to the electron/hole gas to cause the carriers to flow through the transistor.
Preferably the dimensions of the primary portion of the second gate electrode are such that it is less than substantially 100 nm in width measured along an axis perpendicular to the drain and the source. More preferably less than 75 nm and most preferably less than substantially 50 nm.
The transistor may be fabricated so that the primary charge carriers may be either holes or electrons. That is the device may be fabricated so that it is p-type or n-type. This has the advantage that circuits could potentially be fabricated from a number of transistors according to the invention such that the device would use complementary technology similar to the philosophy behind CMOS technology. As the skilled person will realise this is advantageous in that such devices are low power because they have substantially zero quiescent current.
Should the device be fabricated from p-type samples there is the advantage that there is enhanced quantisation in the confined region.
In use, should the primary charge carrier be electrons, the primary portion of the second gate electrode may cause a single potential barrier when a bias voltage is applied between the first and second gates. (Conversely if the primary charge carriers are holes a single potential well may be caused when a voltage is applied between the first and second gate).
It may be possible to cause an equivalent potential barrier or well within a non-narrow band gap semi-conductor by applying high gate bias potentials. However, the gradient of the potential field would be such that electrons could not be held within the field; any electron within the well or barrier would be able to Zener tunnel out of the region. That is, the wave function would leak out of the well or barrier, due to the steepness of the sides.
With a sufficiently high gate (first gate to second gate) bias voltage unoccupied quantised energy levels will occur in the valence band below the primary portion of the second gate electrode. These energy levels may be occupied by charge carriers tunnelling from the conduction band to the valence band (Zener tunnelling).
Narrow band gap may be defined as a material having a valence band at an appropriate level to complement the conduction band such that electrons can use the valence band to tunnel in the manner described hereinbefore. An alternative or additional definition of narrow band gap may be the use of a material having a band gap of less than substantially 1 eV between the conduction and valence bands. Most preferably a band gap of less than substantially xc2xd eV may exist between the conduction and valence bands.
Should the heterojunction be provided as a layer of first material between two layers of second material, the layers may be arranged such that a permanent strain is caused throughout the layer of first material. This is advantageous because it may shift the energy of heavy holes within the valence band such that electrons tunnelling through the transistor can only utilise light holes. As a result of this it is likely that the performance of an n-type device will be as good as the p-type device due to the low effective mass of the light holes.
According to a second aspect of the invention there is provided a method of holding a charge carrier within a quantum dot created by a pair of gate electrodes across a heterojunction, in which a bias voltage applied across the gate electrodes cause a single potential barrier or well within a sheet of charge near the heterojunction such that one or more charge carriers are confined within the barrier or well.
Preferably the method comprises using narrow band gap semi-conductors to provide the sheet of charge. These may show the necessary physical properties to allow the single maxima or minima of field to be provided, in which a charge carrier can be held within.
A potential barrier would be caused in an n-type device and a potential well would be caused in a p-type device.
The method may comprise cooling the heterojunction, for example to substantially liquid nitrogen temperatures (77K). The method may comprise cooling the heterojunction to below liquid nitrogen temperatures, perhaps to substantially liquid helium temperatures (4K).
As discussed in the introduction such cooling may bring the thermal energy of the charge carriers below the charging energy of the quantum dot.
The method may comprise applying a bias along the heterojunction (between a source and drain electrode) such that charge carriers are caused to flow along the heterojunction when potential caused by the gate electrodes allows.
According to a third aspect of the invention there is provided a method of detection comprising using a charge detector wherein the gate electrodes of a field effect transistor according to the first aspect of the invention are connected to a potential source which is representative of the quantity being detected such that variations in the quantity causes variations in the potential applied to the gate electrodes which, in turn, causes a change in current flowing through the transistor.
An advantage of such a device is that the effect may be used directly to measure small changes in an electric field (perhaps this can be thought of as a sensitive electrometer).
Preferably the change of current caused is on an order substantially equal to the original current flowing through the transistor.
Further possible applications may be the formation of an accelerometer or may be of a pressure sensor. The forces exerted on a Zener SET may be enough to alter the physical dimensions of the potential barrier or well. This may change the energy of a quantised level in the valence band relative to the Fermi energy (the energy levels are a function of geometry as well as a function of applied bias voltage) thus causing a change in the current flow through the device.
The method may have a sensitivity comparable with that of a scanning electron microscope.
According to a fourth aspect of the invention there is provided a single electron transistor which relies on Zener Tunnelling of electrons into the valence band of the semi-conductor material from which it is fabricated, to provide transistor action.
According to a fifth aspect of the invention there if provided a single electron transistor in which the energy levels of heavy holes within the valence band are shifted below the energy levels of light holes.
This has the advantage that only light holes are used as electrons tunnel into the valence band so that it is likely the performance of an n-type device will be as good as the p-type device due to the low effective mass of the light holes.
Preferably the energy level of the energy levels of heavy holes are shifted by applying a permanent strain to a material in which electron confinement occurs.
Preferably the material in which the electron confinement occurs in a narrow band gap semi-conductor, which may be provided between two layers of wide band gap semi-conductor.
The strain may be applied to the narrow band gap semi-conductor by lattice strain caused by interaction with the wide band gap semi-conductor.